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| STE2004 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER 1 FEATURES 102 x 65 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode Row by Row Scrolling N-Line Inversion Automatic data RAM Blanking procedure Selectable Input Interface: * I2C Bus Fast and Hs-mode (read and write) * 68000 & 8080 Parallel Interfaces (read and write) * 3-lines and 4-lines SPI Interface (read and write) * 3-lines 9 bit Serial Interface (read and write) Fully Integrated Oscillator requires no external components CMOS Compatible Inputs Fully Integrated Configurable LCD bias voltage generator with: * Selectable multiplication factor (up to 5X) * Effective sensing for High Precision Output * Eight selectable temperature compensation coefficients Designed for chip-on-glass (COG) applications. Low Power Consumption, suitable for battery operated systems Logic Supply Voltage range from 1.7 to 3.6V High Voltage Generator Supply Voltage range from 1.75 to 4.5V Display Supply Voltage range from 4.5 to 14.5V Backward Compatibility with STE2001/2 2 DESCRIPTION The STE2004 is a low power CMOS LCD controller driver. Designed to drive a 65 rows by 102 columns graphic display, it provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption. STE2004 features six standard interfaces (3-lines Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel, 8080 parallel & I2C) for ease of interfacing with the host micro-controller Table 1. Order Codes Part Numbers STE2004DIE1 STE2004DIE2 Type Bumped Wafers Bumped Dice on Waffle Pack Figure 1. Block Diagram CO to C101 R0 to R64 OSC_IN OSC_OUT FR_IN FR_OUT OSC MASTER SLAVE SYNC BIAS VOLTAGE GENERATOR TIMING GENERATOR CLOCK COLUMN DRIVERS ROW DRIVERS DATA LATCHES SHIFT REGISTER VSENSE SLAVE VLCD VLCDSENSE RES VSSAUX VDD1,2 VSS SEL1,2 SEL 0 DATA REGISTER INSTRUCTION REGISTER RESET HIGH VOLTAGE GENERATOR 65 x 102 RAM SCROLL LOGIC TEST TEST_MODE TEST_VREF ICON_MODE EXT DISPLAY CONTROL LOGIC I2C BUS 9 Bit SERIAL 3 & 4 Line SPI Parallel 8080 Parallel 68K SEL 1 SEL 2 SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD to DB7 D/C CS LR0047 July 2004 Rev. 4 1/66 STE2004 Table 2. Pin Description N R0 to R64 C0 to C101 VSS VDD1 VDD2 VLCD VLCDSENSE VSENSE_SLAVE VSSAUX VDD1AUX SEL1,2,3 Pad 1-6 109-141 6-107 192-203 156-163 164-171 205-209 204 145 190-177147 142 152 153 154 Type O O GND Supply Supply Supply Supply Supply O O I LCD Row Driver Output LCD Column Driver Output Ground pads. IC Positive Power Supply Internal Generator Supply Voltages. Voltage Multiplier Output Voltage Multiplier Regulation Input. VLCDOUT Sensing for Output Voltage Fine Tuning Voltage reference for SLAVE CHARGE PUMP Ground Reference for Pins Configuration VDD1 Reference for Pins Configuration Interface Mode Selection - CANNOT BE LEFT FLOATING SEL3 SEL2 SEL1 GND / VSSAUX VDD1 GND / VSSAUX VDD1 GND / VSSAUX VDD1 Interface I2C SPI 4-Lines 8 bit SPI 3-Lines 8 bit Serial 3-Lines 9 bit Parallel 8080-series Parallel 68000-series GND / VSSAUX GND / VSSAUX GND / VSSAUX GND / VSSAUX GND / VSSAUX GND / VSSAUX VDD1 VDD1 EXT_SET 151 I VDD1 VDD1 GND / VSSAUX GND / VSSAUX Function Extended Instruction Set Selection - CANNOT BE LEFT FLOATING EXT PAD CONFIG INSTRUCTION SET SELECTED GND or VSSAUX VDD1 BASIC EXTENDED ICON_MODE 155 I Extended Instruction Set Selection - CANNOT BE LEFT FLOATING ICON MODE PAD CONFIG ICON MODE STATUS GND or VSSAUX VDD1 DISBLED ENABLED SDOUT SDIN - SDAIN 180 179 O I I Serial & SPI Data Output - IF UNUSED MUST BE LEFT FLOATING SDIN - Serial & SPI Interface Data Input - CANNOT BE LEFT FLOATING SDAIN - I2C Bus Data In - CANNOT BE LEFT FLOATING SCLK - Serial & SPI Interface Clock - CANNOT BE LEFT FLOATING SCL - I2C bus Clock - CANNOT BE LEFT FLOATING I2C Bus Data Out IF UNUSED MUST BE LEFT FLOATING I2C Slave Address BIT 0 - CANNOT BE LEFT FLOATING I2C Slave Address BIT 1- CANNOT BE LEFT FLOATING Parallel Interface 8 Bit Data Bus - CANNOT BE LEFT FLOATING R/W - 68000 Series Parallel Interface Read & Write Control Input - CANNOT BE LEFT FLOATING RD - 8080 Series Parallel Interface Read enable Clock Input - CANNOT BE LEFT FLOATING E - 68000 Series Parallel Interface Read & Write Clock Input - CANNOT BE LEFT FLOATING SCLK - SCL 181 I I SDA_OUT SA0 SA1 DB0 to DB7 R/W - RD 178 149 148 182-189 175 O I I I/O I I E / WR 176 I 2/66 STE2004 Table 2. Pin Description (continued) N E / WR RES D/C CS TEST_MODE TEST_VREF OSCIN Pad 176 172 174 173 191 146 144 Type I I I I I O I Function WR - 8080 Series Parallel Interface - Write enable clock input - CANNOT BE LEFT FLOATING Reset Input. Active Low. Interface Data/Command Selector- CANNOT BE LEFT FLOATING Serial & Parallel Interfaces ENABLE. When Low the Incoming Data are Clocked In. CANNOT BE LEFT FLOATING Test Pad - 50 kohm internal Pull-down MUST BE CONNECTED TO VSS/VSSAUX Test Pad - MUST BE LEFT FLOATING Oscillator Input: OSC_IN High Low External Scillator OSCOUT FR_OUT FR_IN M/S 210 211 143 100 O O I I Configuration Internal Oscillator Enabled Internal Oscillator Disabled Internal Oscillator Disabled Internal/External Oscillator Out - IF UNUSED MUST BE LEFT FLOATING Master Slave Frame Inversion Synchronization. IF UNUSED MUST BE LEFT FLOATING Master Slave Frame Inversion Synchronization. CANNOT BE LEFT FLOATING Master/Slave Configuration Bit:- CANNOT BE LEFT FLOATING M/S PIN High Low OSC_OUT ENABLED ENABLED FR_OUT Enabled Enabled FR_IN Enabled Charge Pump Charge Pump in Slave Mode or Ext Power Disabled AuxVsense Disabled 3/66 STE2004 Figure 2. Chip Mechanical Drawing ROW 27 ROW 5 ROW 6 MARK_1 ROW28 ROW31 ROW 0 COL 0 FR_OUT OSC_OUT MARK_3 STE2004 VLCD VLCDSENSE VSS TEST_MODE VSSAUX D0 D1 D2 D3 D4 D5 D6 D7 SCLK - SCL SDOUT SDIN - SDAIN SDAOUT COL 50 VSSAUX E - WR (0,0) COL 51 Y R/W - RD D/C CS X MARK_4 RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX COL 101 ROW 32 ROW64/ICON ROW63 ROW60 MARK_2 ROW 37 LR0048 ROW 38 4/66 ROW 59 STE2004 Figure 3. Improved ALTH & PLESKO Driving Method VLCD V2 V3 ROW 0 R0 (t) V4 V5 VSS VLCD V2 V3 ROW 1 R1 (t) V4 V5 VSS VLCD V2 V3 COL 0 C0 (t) V4 V5 VSS VLCD V2 V3 COL 1 C1 (t) V4 V5 VSS VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD V1(t) V2(t) Vstate1(t) VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS Vstate2(t) V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD 0 1 2 3 4 5 6 7 8 9 ....... ..... 64 0 1 2 3 4 5 6 7 8 9 ....... ..... 64 FRAME n V1(t) = C1(t) - R0(t) V2(t) = C1(t) - R1(t) FRAME n + 1 D00IN1154 5/66 STE2004 3 CIRCUIT DESCRIPTION 3.1 Supplies Voltages and Grounds VDD2 is supply voltages to the internal voltage generator (see below). If the internal voltage generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the IC. VDD1 supply voltage could be different form VDD2. 2 VLCD V DD2 ------------------------ + 200mV (n + 4) 3.2 Internal Supply Voltage Generator The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display supply voltage generation. The multiplying factor can be programmed to be: Auto, X5, X4, X3, X2, using the 'set CP Multiplication' Command. If Auto is set, the multiplying factor is automatically selected to have the lowest current consumption in every condition. This make possible to have an input voltage that changes over time and a constant VLCD voltage. The output voltage (VLCD) is tightly controlled through the VLCDSENSE pad. For this voltage, eight different temperature coefficients (TC, rate of change with temperature) can be programmed using TC1 & TC0 or T2, T1 and T0 bits. This will ensure no contrast degradation over the LCD operating range. An external supply could be connected to VLCD to supply the LCD without using the internal generator. In such event the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset condition) and the Charge pump (CP[0;0]) set to 5x or Auto Mode. 3.3 Oscillator A fully integrated oscillator (requires no external components) is present to provide the clock for the Display System. When used the OSC pad must be connected to VDD1 pad. An external oscillator could be used and fed into the OSC pin.If an external oscillator is used, it must be always present when STE2004 is not in power down mode. An oscillator out is provided on the OSCOUT Pad to cascade two or more drivers. 3.4 Master/Slave Mode STE2004 support the Master Slave working Mode for Both Control Logic and Charge Pump. This function allows to drive matrix such as 204x65 or 102x130 using two synchronized STE2004 and the internal Charge Pump of both device. If M/S is connected to VDD1, the driver is configured to work in Master Mode. When STE2004 is in Master Mode the Vsense_Slave Pin is disabled and is possible to control the VLCD value using Vop Bits. The Master Time Generator outputs on FR_OUT and on OSC_OUT the relevant timing references. If M/S is connected to GND, the driver is configured to work in Slave Mode. When STE2004 is in Slave Mode, the VLCD configuration set by Vop registers and the thermal compensation slope set by TC register are neglected. The VLCD Value generated is equal to the Voltage value present on Vsense_Slave Pin so the slave configuration can follow the master configuration. The only recognized configuration is Vop=0 that forces the Charge Pump to be in off state whatever is the value of Vsense_aux. To Synchronize the Master & Slave timing circuits, the slave driver FR_IN pad must be connected to Master Driver FR_OUT pad and Slave Driver OSC_IN pad must be connected to the master driver OSC_OUT Pad (Fig. 4). This connection ensure a synchronization at both Frame level (R0 on the master is driven together with the Slave R0 driver) and at Oscillator Level (same Frame frequency on the master and on the slave). If the Synchronization at Frame level is not required, FR_IN pin must be connected toVDD1 or to VDD1_aux (Fig. 5). During Power Up Procesure, Master device must be forced to exit from power down before the slave device. To enter in PowerDown Mode, Slave Device must be forced in Power Down state before Master Device. 6/66 STE2004 Figure 4. Master Slave Logic Connection with frame Synchronization STE2004 VDD1AUX OSCIN FRIN OSCOUT FROUT STE2004 FRIN OSCIN OSCOUT FROUT LR0219 Figure 5. Master Slave Logic Connection without frame Synchronization STE2004 VDD1AUX OSCIN FRIN OSCOUT FROUT VDD1AUX STE2004 OSCIN FRIN OSCOUT FROUT LR0220 3.5 Bias Levels To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are established to be (Fig. 6): n+2 2 1 n+3 V LCD, ------------ V LCD , ------------ V LCD , ------------ V LCD , ------------ V LCD ,V SS n+4 n+4 n+4 n+4 Figure 6. Bias level Generator R VLCD n+3 *VLCD n+4 R n+2 *VLCD n+4 nR 2 *VLCD n+4 R 1 *VLCD n+4 R VSS D00IN1150 thus providing an 1/(n+4) ratio, with n calculated from: n= For m = 65, n = 5 and an 1/9 ratio is set. For m = 49, n =4 and an 1/8 ratio is set. The STE2004 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below: m-3 7/66 STE2004 Table 3. BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 n 7 6 5 4 3 2 1 0 The following table Bias Level for m = 65 and m = 49 are provided: Table 4. Symbol V1 V2 V3 V4 V5 V6 m = 65 (1/9) VLCD 8/9*VLCD 7/9*VLCD 2/9*V VLCD 1/9 *VLCD VSS m = 49 (1/8) VLCD 7/8*VLCD 6/8*VLCD 2/8*VLCD 1/8*VLCD VSS 3.6 LCD Voltage Generation The LCD Voltage at reference temperature (To = 27C) can be set using the VOP register content according to the following formula: VLCD(T=To) = VLCDo = (Ai+VOP * B) with the following values: Symbol Ao A1 A2 B To Value 2.95 6.83 10.71 0.0303 27 Unit V V V V C Note PRS = [0;0] PRS = [0;1] PRS = [1;0] (i=0,1,2) Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits are set to zero the internal voltage generator is switched off. The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Multiplexing Rate. A general expression for this is: 1+ m V LCD = ----------------------------------- V th 1 2 1 - -------- m For MUX Rate m = 65 the ideal VLCD is: VLCD(to) = 6.85 * Vth than: ( 6.85 V th - A i ) V op = ---------------------------------------0.03 8/66 STE2004 3.7 Temperature Coefficients As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need to vary the LCD Voltage with temperature. STE2004 provides the possibility to change the VLCD in a linear fashion against temperature with eight different Temperature Coefficient selectable through T2, T1 and T0 bits. Only four of them are available through basic instruction set. Table 5. NAME TC0 TC2 TC3 TC6 TC1 0 0 1 1 TC0 0 1 0 1 Value -0.0* 10-3 -0.7 * 10-3 -1.05* 10-3 -2.1 * 10-3 Unit 1/ C 1/C 1/C 1/C Table 6. NAME TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 Value -0.0* 10-3 Unit 1/ C 1/C 1/C 1/C 1/C 1/C 1/C 1/C -0.35 * 10-3 -0.7 * 10-3 -1.05* 10-3 -1.4 * 10-3 -1.75* 10-3 -2.1 * 10-3 -2.3* 10-3 Figure 7. VLCD B A0 + B A1 00h 01h 02h 03h 04h 05h .... 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h .... A2 A1 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h .... 7Ch 7Dh 7Eh 7Fh PRS = [0;0] PRS = [0;1] PRS = [1;0] VO Finally, the VLCD voltage at a given (T) temperature can be calculated as: VLCD(T) = VLCDo * [1 + (T-To) * TC] 9/66 STE2004 3.8 Display Data RAM The STE2004, provides an 102X65 bits Static RAM to store Display data. This is organized into 9 (Bank0 to Bank8) banks with 102 Bytes. One of these Banks can be used for Icons. RAM access is accomplished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X101 (Horizontal) and Y0 to Y8 (Vertical). When writing to RAM, four addressing mode are provided: * Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the memory map. The X pointer is increased after each byte written. After the last column address (X=X-Carriage), Y address pointer is set to jump to the following bank and X restarts from X=0. (Fig. 8) * Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), X address pointer is set to jump to next column and Y restarts from Y=0 (Fig. 9). * Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the memory map. The X pointer is increased after each byte written. After the last column address (X=XCarriage), Y address pointer is set to jump to the next bank and X restarts from X=0 (fig. 10). * Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), the X pointer is set to jump to next column and Y restarts from Y=0 (fig. 11). After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jump to the cell with address (X;Y) = (0;0) (Fig. 12,13,14 & 15). Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.16) or on the bottom (D0=1, Fig. 17). The STE2004 provides also means to alter the normal output addressing. A mirroring of the Display along the X axis is enabled setting to a logic one MY bit.This function doesn't affect the content of the memory map. It is only related to the memory read process. When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled. When ICON MODE=0 the Icon Row is like an other graphic line and is mirrored and scrolled. Three are the multiplex ratio available when the partial display mode is disabled (MUX 33, MUX 49 and MUX 65). Only a subset of writable rows are output on Row drivers in MUX 33,49 & 65 Mode. When Y-Carriage 10/66 STE2004 Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)1 0 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8 1 2 3 98 99 100 101 LR0049 Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)1 0 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8 1 2 3 98 99 100 101 LR0050 Figure 10. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)1 101 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8 100 99 98 3 2 1 0 LR0051 Figure 11. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)1 101 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8 100 99 98 3 2 1 0 LR0052 1. X Carriage=101; Y-Carriage = 8 11/66 STE2004 Figure 12. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=0) X CARR 0 BANK 0 BANK 1 BANK 2 1 2 3 98 99 100 101 Y CARR BANK 7 BANK 8 LR0053 Figure 13. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=0) X CARR 0 BANK 0 BANK 1 BANK 2 1 2 3 98 99 100 101 Y CARR BANK 7 BANK 8 LR0054 Figure 14. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=1) X CARR 101 BANK 0 BANK 1 BANK 2 100 99 98 3 2 1 0 Y CARR BANK 7 BANK 8 LR0055 Figure 15. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=1) X CARR 101 BANK 0 BANK 1 BANK 2 100 99 98 3 2 1 0 Y CARR BANK 7 BANK 8 LR0056 12/66 STE2004 Figure 16. Data RAM Byte organization with D0 = 0 MSB 0 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8 1 2 3 98 99 100 101 LSB LR0057 Figure 17. Data RAM Byte organization with D0 = 1 LSB 0 BANK BANK BANK BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 6 7 8 1 2 3 98 99 100 101 MSB LR0058 13/66 STE2004 Figure 18. Memory Rows vs. Row Drivers Mapping ICON_MODE=1 and MUX 65 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 Scrolling Pointer Y-CARRIAGE 0 1 0 0 Page 4 0 1 0 1 Page 5 0 1 1 0 Page 6 0 1 1 1 Page 7 0 0 1 X address 0 Page 8 ROW Output Normal Reverse direction direction R0 R63 R1 R62 R2 R61 R3 R60 R4 R59 R5 R58 R6 R57 R7 R56 R8 R55 R9 R54 R10 R53 R11 R52 R12 R51 R13 R50 R14 R49 R15 R48 R16 R47 R17 R46 R18 R45 R19 R44 R20 R43 R21 R42 R22 R41 R23 R40 R24 R39 R25 R38 R26 R37 R27 R36 R28 R35 R29 R34 R30 R33 R31 R32 R32 R31 R33 R30 R34 R29 R35 R28 R36 R27 R37 R26 R38 R25 R39 R24 R40 R23 R41 R22 R42 R21 R43 R20 R44 R19 R45 R18 R46 R17 R47 R16 R48 R15 R49 R14 R50 R13 R51 R12 R52 R11 R53 R10 R54 R9 R55 R8 R56 R7 R57 R6 R58 R5 R59 R4 R60 R3 R61 R2 R62 R1 R63 R0 R64 R64 lr0268 COL Output Normal Direction Reverse Direction C C O O L L 0 1 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C O L 99 C O L 2 C O L 100 C O L 1 C O L 101 C O L 0 14/66 STE2004 Figure 19. Memory Rows vs. Row Drivers Mapping ICON_MODE=0 and MUX 65 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R64 R1 R63 R2 R62 R3 R61 R4 R60 R5 R59 R6 R58 R7 R57 R8 R56 R9 R55 R10 R54 R11 R53 R12 R52 R13 R51 R14 R50 R15 R49 R16 R48 R17 R47 R18 R46 R19 R45 R20 R44 R21 R43 R22 R42 R23 R41 R24 R40 R25 R39 R26 R38 R27 R37 R28 R36 R29 R35 R30 R34 R31 R33 R32 R32 R33 R31 R34 R30 R35 R29 R36 R28 R37 R27 R38 R26 R39 R25 R40 R24 R41 R23 R42 R22 R43 R21 R44 R20 R45 R19 R46 R18 R47 R17 R16 R48 R49 R15 R50 R14 R51 R13 R52 R12 R53 R11 R54 R10 R55 R9 R56 R8 R57 R7 R58 R6 R59 R5 R60 R4 R61 R3 R62 R2 R63 R1 R64 R0 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 Scrolling Pointer Y-CARRIAGE 0 1 0 0 Page 4 0 1 0 1 Page 5 0 1 1 0 Page 6 0 1 1 1 Page 7 00 1 X address 0 Page 8 COL Output Normal Direction Reverse Direction C C O O L L 1 0 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C O L 99 C O L 2 C O L 100 C O L 1 C O L 101 C O L 0 lr0269 15/66 STE2004 Figure 20. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=6 and MUX 49 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R55 R1 R54 R2 R53 R3 R52 R4 R51 R5 R50 R6 R49 R7 R48 R8 R47 R9 R46 R10 R45 R11 R44 R12 R43 R13 R42 R14 R41 R15 R40 R16 R39 R17 R38 R18 R37 R19 R36 R20 R35 R21 R34 R22 R33 R23 R32 R23 R32 R22 R33 R21 R34 R20 R35 R19 R36 R18 R37 R17 R38 R16 R39 R15 R40 R14 R41 R13 R42 R12 R43 R11 R44 R10 R45 R9 R46 R8 R47 R7 R48 R6 R49 R5 R50 R4 R51 R3 R52 R2 R53 R1 R54 R0 R55 R56 R56 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 Scrolling Pointer 0 1 0 0 Page 4 0 1 0 1 Page 5 Y-CARRIAGE 0 1 1 0 Page 6 0 1 1 1 Page 7 00 1 X address 0 Page 8 COL Output Normal Direction Reverse Direction C C O O L L 1 0 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C O L 99 C O L 2 C O L 100 C O L 1 C O L 101 C O L 0 lr0270 16/66 STE2004 Figure 21. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage<=6 and MUX 49 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R56 R1 R55 R2 R54 R3 R53 R4 R52 R5 R51 R6 R50 R7 R49 R8 R48 R9 R47 R10 R46 R11 R45 R12 R44 R13 R43 R14 R42 R15 R41 R16 R40 R17 R39 R18 R38 R19 R37 R20 R36 R21 R35 R22 R34 R23 R33 R32 R32 R23 R33 R22 R34 R21 R35 R20 R36 R19 R37 R18 R38 R17 R39 R16 R40 R15 R41 R14 R42 R13 R43 R12 R44 R11 R45 R10 R46 R9 R47 R8 R48 R7 R49 R6 R50 R5 R51 R4 R52 R3 R53 R2 R54 R1 R55 R0 R56 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 Scrolling Pointer 0 1 0 0 Page 4 0 1 0 1 Page 5 Y-CARRIAGE 0 1 1 0 Page 6 0 1 1 1 Page 7 00 1 X address 0 Page 8 COL Output Normal Direction Reverse Direction C C O O L L 0 1 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C O L 99 C O L 2 C O L 100 C O L 1 C O L 101 C O L 0 lr0271 17/66 STE2004 Figure 22. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=7, Scrolling Pointer>07h and MUX 49 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 Scrolling Pointer 0 1 0 0 Page 4 0 1 0 1 Page 5 ROW Output Normal Reverse direction direction R0 R56 R1 R55 R2 R54 R3 R53 R4 R52 R5 R51 R6 R50 R7 R49 R8 R48 R9 R47 R10 R46 R11 R45 R12 R44 R13 R43 R14 R42 R15 R41 R16 R40 R17 R39 R18 R38 R19 R37 R20 R36 R21 R35 R22 R34 R23 R33 R32 R32 R23 R33 R22 R34 R21 R35 R20 R36 R19 R37 R18 R38 R17 R39 R16 R40 R15 R41 R14 R42 R13 R43 R12 R44 R11 R45 R10 R46 R9 R47 R8 R48 R7 R49 R6 R50 R5 R51 R4 R52 R3 R53 R2 R54 R1 R55 R0 R56 0 1 1 0 Page 6 Y-CARRIAGE 0 1 1 1 Page 7 00 1 X address 0 Page 8 COL Output Normal Direction Reverse Direction C C OO L L 1 0 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C C C OOO L L L 99 100 101 C CC O OO L LL 0 2 1 lr0275 18/66 STE2004 Figure 23. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=7, Scrolling Pointer>07h and MUX 49 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H ROW Output Normal Reverse direction direction R0 R55 R1 R54 R2 R53 R3 R52 R4 R51 R5 R50 R6 R49 R7 R48 R8 R47 R9 R46 R10 R45 R11 R44 R12 R43 R13 R42 R14 R41 R15 R40 R16 R39 R17 R38 R18 R37 R19 R36 R20 R35 R21 R34 R22 R33 R23 R32 R23 R32 R22 R33 R21 R34 R20 R35 R19 R36 R18 R37 R17 R38 R16 R39 R15 R40 R14 R41 R13 R42 R12 R43 R11 R44 R10 R45 R9 R46 R8 R47 R7 R48 R6 R49 R5 R50 R4 R51 R3 R52 R2 R53 R1 R54 R0 R55 R56 R56 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 Scrolling Pointer 0 1 0 0 Page 4 0 1 0 1 Page 5 0 1 1 0 Page 6 Y-CARRIAGE 0 1 1 1 Page 7 00 1 X address 0 Page 8 COL Output Normal Direction Reverse Direction C C OO L L 1 0 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C C C OOO L L L 99 100 101 C CC O OO L LL 0 2 1 lr0276 19/66 STE2004 Figure 24. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=8, Scrolling Pointer<10h and MUX 49 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H ROW Output Normal Reverse direction direction R0 R55 R1 R54 R2 R53 R3 R52 R4 R51 R5 R50 R6 R49 R7 R48 R8 R47 R9 R46 R10 R45 R11 R44 R12 R43 R13 R42 R14 R41 R15 R40 R16 R39 R17 R38 R18 R37 R19 R36 R20 R35 R21 R34 R22 R33 R23 R32 R23 R32 R22 R33 R21 R34 R20 R35 R19 R36 R18 R37 R17 R38 R16 R39 R15 R40 R14 R41 R13 R42 R12 R43 R11 R44 R10 R45 R9 R46 R8 R47 R7 R48 R6 R49 R5 R50 R4 R51 R3 R52 R2 R53 R1 R54 R0 R55 R56 R56 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H 0 0 0 0 Page 0 Scrolling Pointer 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 0 1 0 0 Page 4 0 1 0 1 Page 5 0 1 1 0 Page 6 0 1 1 1 Page 7 Y-CARRIAGE 00 1 X address 0 Page 8 COL Output Normal Direction Reverse Direction C C OO L L 1 0 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C C C OOO L L L 99 100 101 C CC O OO L LL 0 2 1 LR0273 20/66 STE2004 Figure 25. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=8, Scrolling Pointer<10h and MUX 49 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H ROW Output Normal Reverse direction direction R0 R56 R1 R55 R2 R54 R3 R53 R4 R52 R5 R51 R6 R50 R7 R49 R8 R48 R9 R47 R10 R46 R11 R45 R12 R44 R13 R43 R14 R42 R15 R41 R16 R40 R17 R39 R18 R38 R19 R37 R20 R36 R21 R35 R22 R34 R23 R33 R32 R32 R23 R33 R22 R34 R21 R35 R20 R36 R19 R37 R18 R38 R17 R39 R16 R40 R15 R41 R14 R42 R13 R43 R12 R44 R11 R45 R10 R46 R9 R47 R8 R48 R7 R49 R6 R50 R5 R51 R4 R52 R3 R53 R2 R54 R1 R55 R0 R56 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H 0 0 0 0 Page 0 Scrolling Pointer 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 0 1 0 0 Page 4 0 1 0 1 Page 5 0 1 1 0 Page 6 0 1 1 1 Page 7 Y-CARRIAGE 00 1 X address 0 Page 8 COL Output Normal Direction Reverse Direction C C OO L L 1 0 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C C C OOO L L L 99 100 101 C CC O OO L LL 0 2 1 LR0274 21/66 STE2004 Figure 26. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=4 and MUX33 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H ROW Output Normal Reverse direction direction R0 R47 R1 R46 R2 R45 R3 R44 R4 R43 R5 R42 R6 R41 R7 R40 R8 R39 R9 R38 R10 R37 R11 R36 R12 R35 R13 R34 R14 R33 R15 R32 R15 R32 R14 R33 R13 R34 R12 R35 R11 R36 R10 R37 R9 R38 R8 R39 R7 R40 R6 R41 R5 R42 R4 R43 R3 R44 R2 R45 R1 R46 R0 R47 R48 R48 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 Scrolling Pointer 0 0 1 1 Page 3 Y-CARRIAGE 0 1 0 0 Page 4 0 1 0 1 Page 5 0 1 1 0 Page 6 0 1 1 1 Page 7 00 1 X address 0 Page 8 COL Output Normal Direction Reverse Direction C C OO L L 0 1 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C C C OOO L L L 99 100 101 C CC O OO L LL 0 2 1 LR0272 22/66 STE2004 Figure 27. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage<=4 and MUX 33 Y Address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 5FH 60H 61H 62H 63H 64H 65H ROW Output Normal Reverse direction direction R0 R48 R1 R47 R2 R46 R3 R45 R4 R44 R5 R43 R6 R42 R7 R41 R8 R40 R9 R39 R10 R38 R11 R37 R12 R36 R13 R35 R14 R34 R15 R33 R32 R32 R15 R33 R14 R34 R13 R35 R12 R36 R11 R37 R10 R38 R9 R39 R8 R40 R7 R41 R6 R42 R5 R43 R4 R44 R3 R45 R2 R46 R1 R47 R0 R48 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 Scrolling Pointer 0 0 1 1 Page 3 Y-CARRIAGE 0 1 0 0 Page 4 0 1 0 1 Page 5 0 1 1 0 Page 6 0 1 1 1 Page 7 00 1 X address 0 Page 8 COL Output Normal Direction Reverse Direction C C OO L L 1 0 C C O O L L 101 100 C O L 2 C O L 99 C O L 3 C O L 98 C O L 4 C O L 97 C O L 5 C O L 96 C O L 6 C O L 95 C O L 95 C O L 6 C O L 96 C O L 5 C O L 97 C O L 4 C O L 98 C O L 3 C C C OOO L L L 99 100 101 C CC O OO L LL 0 2 1 LR0272 23/66 STE2004 Figure 28. Row Drivers vs. LCD Panel Interconnection in MUX65 Mode ICON MUX 65 COLUMN DRIVERS R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 ROW DRIVERS STE2004 ROW DRIVERS LR0109 Figure 29. Row Drivers vs. LCD Panel Interconnection in MUX49 Mode ICON MUX 49 COLUMN DRIVERS R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 ROW DRIVERS STE2004 ROW DRIVERS LR0108 24/66 STE2004 Figure 30. Row Drivers vs. LCD Panel Interconnection in MUX33 Mode ICON MUX 33 COLUMN DRIVERS R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 ROW DRIVERS ROW DRIVERS STE2004 LR0107 25/66 STE2004 4 BUS INTERFACES To provide the widest flexibility and ease of use the STE2004 features Six different methods for interfacing the host Controller. To select the desired interface the SEL1, SEL2 and SEL3 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused interfaces must be connected to GND. All interfaces are working while the STE2004 is in Power Down. Table 7. SEL3 0 0 0 0 1 1 SEL2 0 0 1 1 0 0 SEL1 0 1 0 1 0 1 I2C SPI 4 lines 8 bit SPI 3 lines 8 bit Serial 3 lines 9 bit Parallel 8080-series Parallel 68000-series Interface Note Read and Write; Fast and High Speed Mode Read and Write Read and Write Read and Write Read and Write Read and Write 4.1 I2C Interface The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock) and High Speed Mode (3.4MHz). This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via an active or passive pull-up. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: BUS not busy: Both data and clock lines remain High. Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the START condition. Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High, defines the STOP condition. Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and the stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with the ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves" Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked 26/66 STE2004 out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2004 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. To be compliant with the I2C-bus Hs-mode specification the STE2004 is able to detect the special sequence "S00001xxx". After this sequence no acknowledge pulse is generated. Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without detecting the master code. Figure 31. Bit transfer and START,STOP conditions definition DATA LINE STABLE DATA VALID CLOCK DATA START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION LR0069 Figure 32. Acknowledgment on the I2C-bus START SCLK FROM MASTER CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9 DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER MSB LSB LR0070 4.1.1 Communication Protocol The STE2004 is an I2C slave. The access to the device is bi-directional since data write and status read are allowed. Four are the device addresses available for the device. All have in common the first 5 bits (01111). The two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or to a logic 1. To start the communication between the bus master and the slave LCD driver, the master must initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA bus line (Most significant bit first). This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/W). All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer. 27/66 STE2004 4.1.2 Writing Mode. If the R/W bit is set to logic 0 the STE2004 is set to be a receiver. After the slaves acknowledge one or more command word follows to define the status of the device. A command word is composed by three bytes. The first is a control byte which defines the Co and D/C values, the second and third are data bytes. The Co bit is the command MSB and defines if after this command will follow two data bytes and an other command word or if will follow a stream of data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/C = 0 Command). If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following data byte will be stored in the data RAM at the location specified by the data pointer. Every byte of a command word must be acknowledged by all addressed units. After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2004 Display RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every byte written and in the end points to the last RAM location written. Every byte must be acknowledged by all addressed units. 4.1.3 Reading Mode. If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit during the last write access, is set to a logic 0, the byte read is the status byte. Figure 33. Communication Protocol WRITE MODE DRIVER ACK DRIVER ACK DRIVER ACK DRIVER ACK DRIVER ACK SS S 0 1 1 1 1 A A 0 A 1 DC Control Byte A 10 R/W Co SLAVE ADDRESS READ MODE DRIVER ACK SS S01111AA1A 10 R/W DATA Byte A 0 DC Control Byte A DATA Byte AP Co COMMAND WORD LAST CONTROL BYTE N> 0 BYTE MSB........LSB MASTER ACK SSR 01111AA / 1 0W DRIVER SLAVE ADDRESS P HHH CD 000 A E [1] [0] oC CONTROL BYTE LR0008 4.2 SERIAL INTERFACES STE2004 can feature three different serial synchronized interfaces with the host controller. It is possible to select a 3-lines SPI, a 4-lines SPI or 3-line 9 bits Serial Interface. 4.2.1 4-lines SPI interface STE2004 4-lines serial interface is a bidirectional link between the display driver and the application supervisor. It consists of four lines: one/two for data signals (SDIN, SOUT), one for clock signals (SCLK), one for the peripheral enable (CS) and one for mode selection (SD/C). The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral power consumption is zero. While CS pin is high the serial interface is kept in reset. The STE2004 is always a slave on the bus and receive the communication clock on the SCLK pin from the master. Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge. SD/C line status indicates whether the byte is a command (SD/C =0) or a data (SD/C =1); SD/C line is read on 28/66 STE2004 the eighth SCLK clock pulse during every byte transfer. If CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte at the next SCLK positive edge. A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal registers are cleared. If CS is low after the positive edge of RES, the serial interface is ready to receive data. Throughout SDOUT can be read the driver I2C slave address or the status byte. The Command sequence that allows to read I2C slave address or Status byte is reported in Fig. 34 & 35. SDOUT is in High impedance in steady state and during data write. It is possible to short circuit SDOUT and SDIN and read I2C address or status Byte without any additional lines. Figure 34. 4-lines serial bus protocol - one byte transmission CS D/C SCLK SDIN MSB LSB LR0071 Figure 35. 4-lines serial bus protocol - several byte transmission CS D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 LR0072 Figure 36. 4-lines serial bus protocol - I2C Address or Status Byte Read CS SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care D/C High-Z SDOUT High-Z DB7 DB6 High-Z DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ID Number DB5 DB4 DB3 DB2 DB1 DB0 High-Z STATUS BYTE Command Write DATA Read LR00076 29/66 STE2004 Figure 37. 4-lines SPI Reading Sequence READING SEQUENCE Write a "00000000" Instruction SDOUT Buffer becomes active (Low Impedence) Source 8 pulses on SCLK and 1 Read the ID Number or the Status Byte On SDOUT SDOUT Buffer Configured in High Impedence END OF READING SEQUENCE note: 1) these data are not read by the display Diver 2) SDIN and SDOUT can be short circuited if the processor can configure serial output buffers in high impedence during data read. LR0078 4.2.2 3-lines SPI Interface The STE2004 3-lines serial Interface is a bidirectional link between the display driver and the application supervisor. It consists of three lines: one/two for data signals (SDIN,SDOUT), one for clock signals (SCLK) and one for peripheral enable (CS). If the R/W bit is set to logic 0 the STE2004 is set to be a receiver. One or more command word follows to define the status of the device. A command word is composed by two bytes. The first is a control byte which defines Co, D/C, R/W H[1;0] and HE values, the second is a data byte (fig 39). The Co bit is the command MSB and defines if after this command will follow one data byte and an other command word or if will follow a stream of Commands or a Steam of DDRAM Data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether the data byte is a command or DDRAM data (D/C = 1 RAM Data, D/C = 0 Command). The H[1;0] bits define the instruction Set Page if HE bit =1. If HE bit is set to 0 H[1;0] values are neglected and it is possible to update the instruction set page number using only the related instruction in the instruction Set. If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following data byte will be stored in the data RAM at the location specified by the data pointer. After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2004 Display Data RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every byte written and in the end points to the last RAM location written. Throughout SDOUT can be read the driver I2C slave address or the status Byte. The Command sequence that allows to read I2C slave address or the Status byte is reported in Fig. 39 & 40. If the R bit is set to logic 0 and D/C=0, the I2C slave address is read; If the R bit is set to logic 1 and D/ C=0, the the I2C slave address is read SDOUT is in High impedance in steady state and during data write. It is possible to short circuit SDOUT and SDIN and read I2C address or status byte without any additional line. 30/66 STE2004 Figure 38. 3-lines serial interface protocol in Writing Mode WRITE MODE R HHH CD /00 E [1] [0] o CW CONTROL BYTE 1 Control Byte DATA Byte 0 Control Byte DATA Byte Co COMMAND WORD Co LAST CONTROL BYTE N> 0 BYTE MSB........LSB Control Byte 00 DATA Byte DATA Byte TRANSFERRED ONLY COMMANDS DATA Byte = Command if D/C=0 LAST CONTROL BYTE Control Byte 01 N> 0 BYTE MSB........LSB DATA Byte = DDRAM Data if D/C=1 DATA Byte DATA Byte TRANSFERRED ONLY DDRAM DATA LAST CONTROL BYTE N> 0 BYTE MSB........LSB LR0002 Figure 39. 3-lines SPI interface protocol in Reading Mode CS SCLK Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care SDIN DB7 Co=1 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C=0 R/W=1 "Command" "Read" High-Z DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 High-Z SDOUT High-Z DB7 DB6 ID-Number DB5 DB4 DB3 DB2 DB1 DB0 High-Z STATUS BYTE Command Write DATA Read LR0077 31/66 STE2004 Figure 40. 3-lines SPI Reading Sequence READING SEQUENCE Set Co bit =1, D/C Bit =0 R/W Bit =1 SDOUT Buffer become active (Low Impedence) Source 8 pulses on SCLK and 1 Read the ID-Number or the Status Byte On SDOUT SDOUT Buffer Configured in High Impedence END OF READING SEQUENCE note: 1) these data are not read by the display Diver 2) SDIN and SDOUT can be short circuited if the processor can configure serial output buffers in high impedence during data read. LR0079 4.2.3 3-lines 9 bits Serial Interface The STE2004 3-lines serial Interface is a bidirectional link between the display driver and the application supervisor. It consists of three lines: one/two for data signals (SDIN, SDOUT), one for clock signals (SCLK) and one for peripheral enable (CS). The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral power consumption is zero. While CS pin is high the serial interface is kept in reset. The STE2004 is always a slave on the bus and receive the communication clock on the SCLK pin from the master. Information are exchanged word-wide. The word is composed by 9 bit. The first bit is named SD/C and indicates whether the following byte is a command (SD/C =0) or Data Byte (SD/C =1). During data transfer, the data line is sampled on the positive SCLK edge. If CS stays low after the last bit of a command/data byte, the serial interface expects the SD/C Bit of the next word at the next SCLK positive edge. A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal registers are cleared. If CS is low after the positive edge of RES, the serial interface is ready to receive data. Throughout SDOUT can be read only the driver I2C slave address or the status byte. The Command sequence that allows to read I2C slave address or Status byte is reported in Fig. 43 & 44. SDOUT is in High impedance in steady state and during data write. It is possible to short circuit SDOUT and SDIN and read I2C address or status byte without any additional line. 32/66 STE2004 Figure 41. 3-lines serial bus protocol - one byte transmission CS SCLK SDIN SD/C MSB LSB LR0073 Figure 42. 3-lines serial bus protocol - several byte transmission CS SCLK SDIN D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 LR0074 Figure 43. 3-lines serial interface protocol in Reading Mode CS SCLK Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care SDIN SD/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 High-Z SDOUT High-Z DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 High-Z ID-Number DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 High-Z STATUS BYTE Command Write DATA Read LR0075 Figure 44. 3-lines Serial Reading Sequence READING SEQUENCE Write a "00000000" Instruction SDOUT Buffer becomes active (Low Impedence) Source 9 pulses on SCLK and 1 Read the ID Number or the Status Byte On SDOUT SDOUT Buffer Configured in High Impedence END OF READING SEQUENCE note: 1) these data are not read by the display Diver 2) SDIN and SDOUT can be short circuited if the processor can configure serial output buffers in high impedence during data read. LR0080 33/66 STE2004 4.3 Parallel Interface The STE2004 selectable parallel Interfaces are 68000-series and 8080-series. They are both an 8-bits bidirectional link between the display driver and the application supervisor. Throughout both parallel interfaces can be read the I2C driver slave address or the Status Byte. 4.3.1 68000-series parallel interface If CS is low after the positive edge of RES, the 68000 parallel interface is ready to receive or transmit data. While CS pin is high the 68000 Parallel interface is kept in reset. 4.3.2 Write Mode If R/W line is set to 0 Data are latched on E falling edge. 4.3.3 Read Mode When R/W line is set to 1, data are output on D0-D7 bus on E rising edge. Data Bus is set in high impedance mode when E is set to logic 0. Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus. Figure 45. 68000-series Parallel interface protocol - one byte transmission CS R/W D/C E D0 to D7 LR0004 Figure 46. 68000-series Parallel interface bus protocol - Several bytes transmission CS R/W D/C E D0 to D7 LR0081 34/66 STE2004 Figure 47. 68000-series Parallel interface protocol in Reading Mode CS D/C R/W E D0 to D7 LR0082 Figure 48. 68000-series Parallel interface protocol in Reading Mode (Several Bytes) CS D/C R/W E D0 to D7 Note 1) Data Bus is configured in high impedence mode after evry RD rising edge 2) Always the same data is output on D0-D7 LR0046 4.3.4 8080-series parallel interface If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or transmit data. While CS pin is high the 8080 Parallel interface is kept in reset. Write Mode Data are latched on WR rising edge. Read Mode Data are output on D0-D7 bus on RD rising edge. Data Bus is set in high impedance mode when RD is set to logic 1. Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus. Figure 49. 8080-series parallel bus protocol - one byte transmission CS D/C RD WR D0 to D7 LR0083 35/66 STE2004 Figure 50. 8080-series parallel bus protocol - several bytes transmission CS D/C RD WR D0 to D7 LR0084 Figure 51. 8080-series Parallel interface protocol in Reading Mode CS D/C RD WR D0 to D7 LR0085 Figure 52. 8080-series Parallel interface protocol in Reading Mode (Several Bytes) CS D/C RD WR D0 to D7 LR0045 Note 1) Data Bus is configured in high impedence mode after every RD rising edge 2) Always the same data is output on D0-D7 36/66 STE2004 5 INSTRUCTION SET Two different instructions formats are provided: - With D/C set to LOW : commands are sent to the Control circuitry. - With D/C set to HIGH : the Data RAM is addressed. Two different instruction set are embedded: the STE2001-like instruction set and the extended instruction set. To select the STE2001-like instruction set the EXT pad has to be connected to a logic LOW (connect to GND). To select the he extended instruction the EXT pad has to be connected to a logic HIGH (connect to VDD1). The instructions have the syntax summarized in Table 1 (basic-set) and Table 2 (extended set) 5.1 Reset (RES) At power-on, all internal registers are configured with the default value. The RAM content is not defined. A Reset pulse on RES pad (active low) re-initialize the internal registers content (see Tables 3,4,5,&6). Every on-going communication with the host controller is interrupted, applying a reset pulse. After the power-on, the Software Reset instruction can be used to re-load the reset configuration into the internal registers. The Default configurations is: - Horizontal addressing (V = 0) - Normal instruction set (H[1:0] = 0) - Normal display (MX = MY = 0) - Display blank (E = D = 0) - Address counter X[6: 0] = 0 and Y[4: 0] = 0 - Temperature coefficient (TC[1: 0] = 0) - Bias system (BS[2: 0] = 0) - Multiplexing Ratio (M[1:0]=0 - MUX 65) A MEMORY BLANK instruction can be executed to clear the DDRAM content. 5.2 Power Down (PD = 1) When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator are OFF (VLCDOUT output is discharged to VSS, and then is possible to disconnect VLCDOUT). The internal Oscillator is in off state. An external clock can be provided. The RAM contents is not cleared. 5.3 Memory Blanking Procedure This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly generated in memory when starting up the device. This instruction substitutes (102X8) single "write" instructions. It is possible to program "Memory Blanking Procedure" only under the following conditions: - PD bit =0 No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock). The start of Memory blanking procedure will be between one and two fclock cycles from the last active edge (E fallig edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL rising edge for the I2C interface). 5.4 Checker Board Procedure This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended to developers, who can now simply obtain complex module test configuration by means of a single instruction. It is possible to program "Checker Board Procedure" only under the following conditions: - PD bit =0 37/66 - Frame Rate (FR[1:0]="75Hz") - Power Down (PD = 1) - Dual Partial Display Disabled (PE=0) - VOP=0 - Y-CARRIAGE=8 - X-CARRIAGE=101 STE2004 No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock). The start of Checker-board procedure will be between one and two fclock cycles from the last active edge (E falling edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL rising edge for the I2C interface). 5.5 Scrolling Function The STE2004 can scroll the graphics display in units of raster-rows. The scrolling function is achieved changing the correspondence between the rows of the logical memory map and the output row drivers. The scroll function doesn't affect the data ram content. It is only related to the visualization process. The information output on the drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every scrolling command the offset between the memory address and the memory scanning pointer is increased or decreased by one. The offset range changes in accordance with MUX Rate. After 64th/65th scrolling commands in MUX 65 mode, or after the 48th/49th scrolling commands in mux 49 mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the memory address and the memory scanning pointer is again zero (Cyclic Scrolling). A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the memory address and the memory scanning pointer If ICON MODE =1, the Icon Row is not scrolled. If ICON MODE=0 the last row is like a general purpose row and it is scrolled as other lines. If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up. Table 8. MUX RATE MUX 33 MUX 33 MUX 49 MUX 49 MUX 65 MUX 65 ICON MODE 1 0 1 0 1 0 DESCRIPTION ICON ROW NOT SCROOLED 33 LINE GRAPHIC MATRIX ICON ROW NOT SCROOLED 49 LINE GRAPHIC MATRIX ICON ROW NOT SCROOLED 65 LINE GRAPHIC MATRIX ICON Row Driver with MY=0 R48 R48 R56 R56 R64 R64 5.6 Dual Partial Display If the PE Bit is set to a logic one the dual partial display mode is enabled. Eight partial display modes are available. The offset of the two partial display zones is row by row programmable. The Icon row is accessed last in each partial display frame. Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0], BS[2:0], CP[2:0].). This allows switching from normal mode to partial display mode only with one instruction. The HV generator is automatically re configured using the parameters related to the enabled mode. The parameters of the two sets of registers with the same function are located in the same position of the instruction set. The registers related to the normal mode are accessible when normal mode (PE=0) is selected, the others are accessible when the partial display mode is enabled (PE=1). To Setup PRS[1:0], Vop[6:0], BS[2:0], CP[2:0] values the instruction flow proposed in Fig. 54 must be followed. To setup Partial Display Sectors Start Address and Partial Display Mode no particular instruction flow has to be followed. 38/66 STE2004 Figure 53. Dual Partial Display Enabling Instruction Flow ENABLE DUAL PARTIAL DISPLAY SET 1st Sector Start Address SET 2nd Sector Start Address OPTIONAL1 SET PE=1 END OF ENABLING DUAL PARTIAL DISPLAY Figure 54. Dual Partial Display Mode configuration or Duty Change SETUP PARTIAL DISPLAY CONFIGURATION SET Driver in Power Down(PD=1) SET Driver in Partial Display Mode (PE=1) SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0] for Partial Display Operation SET Partial Display Configuration (PDC[2:0]) SET 1st Sector Start Address SET 2nd Sector Start Address OPTIONAL SET Driver in Normal Mode (PE=0) END OF PARTIAL DISPLAY CONFIG. Table 9. Partial Display Configurations PDC 2 0 0 0 0 1 1 1 1 PDC 1 0 0 1 1 0 0 1 1 PDC 0 0 1 0 1 0 1 0 1 SECTION 1 0 8 8 0 16 8 16 16 SECTION2 8 + Icon Row 0 + Icon Row 8 + Icon Row 16 + Icon Row 0 + Icon Row 16 + Icon Row 8 + Icon Row 16 + Icon Row RESET STATE 000 39/66 STE2004 6 ID-NUMBER The STE2004 allows to program a Driver Identification Number (ID-Number). This make possible to easily manage on one platform more than one LCD module with different configuration parameters. Four are the device ID-Numbers programmable: 00111100, 00111101, 0011110 & 0011111. All have in common the first 6 bits (001111). The two least significant bit could be set connecting the SA0 and SA1 inputs to a VSS or VDD1. The driver ID-number can be read through all communication interfaces. The way to read-out the ID-Number changes according the interface selected. The readout protocol for each interface is described in the Bus interfaces paragraph. Table 10. STE2001/2-like instruction Set Instruction H=0 or H=1 Read Commnad Function Set Status Byte ID Code Write Data H=0 Memory Blank Scroll VLCD Range Setting Display Control Set CP Factor Set RAM Y Set RAM X H=1 Checker Board Duty TC Select Data Order Bias Ratios Reserved Set VOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 X 0 0 0 0 1 X 0 0 0 1 0 X 0 0 1 DO X 0 1 0 X 1 MUX 0 Set desired Bias Ratios Not to be used VOP register Write instruction X Starts Checker Board Procedure Selects Duty factor 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X6 0 0 0 0 0 0 X5 0 0 0 0 1 0 X4 0 0 0 1 0 Y3 X3 0 0 1 D S2 Y2 X2 0 1 0 0 S1 Y1 X1 1 DIR Starts Memory Blank Procedure Scrolls by one Row UP or DOWN 0 0 0 0 1 0 0 1 1 0 0 0 PD 0 D7 0 0 BSY 0 D6 0 1 0 1 D5 0 MX D 1 D4 0 MY E 1 D3 0 PD MX 1 D2 0 V MY ID1 D1 0 Read I2C Address or Status Byte (with 3-Lines Serial & 4-lines SPI only) D/C R/W B7 B6 B5 B4 B3 B2 B1 B0 Description H[0] Power Down Management; Entry Mode; DO ID0 D0 Writes data to RAM (I2C interface only) PRS VLDC programming range selection [0] E S0 Y0 X0 Select Display Configuration Charge Pump Multiplication factor Set Horizontal (Y) RAM Address Set Vertical (X) RAM Address TC1 TC0 Set Temperature Coefficient for VLDC BS2 BS1 BS0 OP6 OP5 OP4 OP3 OP2 OP1 OP0 40/66 STE2004 Table 11. Extended Instruction Set Instruction D/C R/W B7 Read Command 0 0 Status Byte ID Code Write Data Memory Blank Scroll VLCD Range Setting Display Control Set CP Factor Set RAM Y Set RAM X Checker Board TC Select Data Order Bias Ratios Read Mode, Set VOP Driver Control Display Control 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Partial Mode 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD 0 D7 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 B6 0 0 BSY 0 D6 0 0 0 0 0 1 X6 0 0 0 0 0 1 B5 0 1 0 1 D5 0 0 0 0 0 0 X5 0 0 0 0 0 0 B4 0 MX D 1 D4 0 0 0 0 1 0 X4 0 0 0 0 1 0 B3 0 MY E 1 D3 0 0 0 1 0 Y3 X3 0 0 0 1 0 R B2 0 PD MX 1 D2 0 0 1 D S2 Y2 X2 0 0 1 DO 0 B1 0 B0 0 Read I2C Address or Status Byte (with 3-Lines Serial & 4-lines SPI only) Page selector, Power Down Management; Entry Mode H Independent Instructions Description H[1] H[0] MY ID1 D1 0 1 DO ID0 D0 1 DIR Writes data to RAM Starts Memory Blank Procedure Scrolls by one Row UP or DOWN VLDC programming range selection Select Display Configuration Charge Pump Multiplication factor Set Horizontal (Y) RAM Address Set Vertical (X) RAM Address Starts Checker Board Procedure Vertical Addressing Mode MSB Position Set desired Bias Ratios VOP register Write instruction Software RESET Partial Enable Frame rate Control Mux Ratio Partial Display Config 1st Sector Start Address 2nd Sector Start Address H=[0;0] RAM Commands PRS PRS [1] [0] 0 S1 Y1 X1 0 1 0 0 E S0 Y0 X0 1 V 0 0 H=[0;1] TC1 TC0 Set Temperature Coefficient for VLDC BS2 BS1 BS0 OP6 OP5 OP4 OP3 OP2 OP1 OP0 H=[1;0] 0 0 0 0 0 1 PD Y6 0 0 0 0 0 1 0 0 0 0 0 PD Y5 PD Y5 0 0 0 0 0 0 0 0 0 0 1 PD Y4 PD Y4 0 0 0 0 1 0 0 0 0 1 0 PD Y3 PD Y3 0 0 0 1 0 0 1 0 0 1 1 PE FR1 FR0 M[1] M[0] PDC PDC PDC 2 1 0 PD Y2 PD Y2 0 0 1 T2 PD Y1 PD Y1 0 1 X T1 PD Y0 PD Y0 1 X X T0 H=[1;1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Scrolling Pointer Reset Not Used Not Used Set Temperature Coefficient for VLDC N-Line Inversion Y-CARRIAGE RETURN X CARRIAGE RETURN NW3 NW2 NW1 NW0 YC-3 YC-2 YC-1 YC-0 XC-6 XC-5 XC-4 XC-3 XC-2 XC-1 XC-0 41/66 STE2004 Table 12. Explanations of Table 3 & 4 symbols BIT DIR H[0] PD V MX MY DO PE MUX R 0 Scroll by one down Select page 0 Device fully working Horizontal addressing Normal X axis addressing Image is displayed not vertically mirrored MSB on TOP Partial Display disabled MUx 65 Mode Read ID-Number / I2C Address 1 Scroll by one up Select page 1 Device in power down Vertical addressing X axis address is mirrored. Image is displayed vertically mirrored MSB on BOTTOM Partial Display enabled MUX 33 Mode Read Status Byte 0 1 0 0 0 0 0 0 0 RESET STATE Table 13. PAGE SELECTION H[1] 0 0 1 1 H[0] 0 1 0 1 Page 0 Page 1 Page 2 Page 3 Page 0 DESCRIPTION RESET STATE Table 14. DISPLAY MODE D 0 0 1 1 E 0 1 0 1 display blank all display segments on normal mode inverse video mode E=0 D=0 DESCRIPTION RESET STATE Table 15. FRAME RATE CONTROL FR[1] 0 0 1 1 FR[0] 0 1 0 1 DESCRIPTION 65Hz 70Hz 75Hz 80Hz 75Hz RESET STATE Table 16. VLCD RANGE SELECTION PRS[1] 0 0 1 1 PRS[0] 0 1 0 1 DESCRIPTION 2.94 6.78 10.62 10.62 RESET STATE 42/66 STE2004 Table 17. MULTIPLEXING RATIO M[1] 0 0 1 1 M[0] 0 1 0 1 DESCRIPTION 49 65 33 Not Allowed 01 RESET STATE Table 18. TEMPERATURE COEFFICIENT T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 DESCRIPTION VLCD temperature Coefficient 0 VLCD temperature Coefficient 1 VLCD temperature Coefficient 2 VLCD temperature Coefficient 3 VLCD temperature Coefficient 4 VLCD temperature Coefficient 5 VLCD temperature Coefficient 6 VLCD temperature Coefficient 7 000 RESET STATE Table 19. TC1 0 0 0 1 TC0 0 1 1 1 DESCRIPTION VLCD temperature Coefficient 0 VLCD temperature Coefficient 2 VLCD temperature Coefficient 3 VLCD temperature Coefficient 6 00 RESET STATE Table 20. CHARGE PUMP MULTIPLICATION FACTOR CP2 0 0 0 0 1 1 1 1 CP1 0 0 1 1 0 0 1 1 CP0 0 1 0 1 0 1 0 1 DESCRIPTION Multiplication Factor X2 Multiplication Factor X3 Multiplication Factor X4 Multiplication Factor X5 NOT USED NOT USED NOT USED AUTOMATIC 000 RESET STATE 43/66 STE2004 Table 21. BIAS RATIO BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 DESCRIPTION Bias Ratio equal to 7 Bias Ratio equal to 6 Bias Ratio equal to 5 Bias Ratio equal to 4 Bias Ratio equal to 3 Bias Ratio equal to 2 Bias Ratio equal to 1 Bias Ratio equal to 0 000 RESET STATE Table 22. Y CARRIAGE RETURN REGISTER Y-C[3] 0 0 0 0 0 . 0 0 1 Y-C[2] 0 0 0 0 1 . 1 1 0 Y-C[1] 0 0 1 1 0 . 1 1 0 Y-C[0] 0 1 0 1 0 . 0 1 0 Y-CARRIAGE =6 Y-CARRIAGE =7 Y-CARRIAGE =8 DESCRIPTION Y-CARRIAGE =0 Y-CARRIAGE =1 Y-CARRIAGE =2 Y-CARRIAGE =3 Y-CARRIAGE =4 1000 RESET STATE Table 23. PARTIAL DISPLAY CONFIGURATION PD2 0 0 0 0 1 1 1 1 PD1 0 0 1 1 0 0 1 1 PD0 0 1 0 1 0 1 0 1 SECTION 1 0 8 8 0 16 8 16 16 SECTION2 8 + Icon Row 0 + Icon Row 8 + Icon Row 16 + Icon Row 0 + Icon Row 16 + Icon Row 8 + Icon Row 16 + Icon Row 000 RESET STATE Table 24. N-LINE INVERSION NW3 0 0 0 0 : 1 1 NW2 0 0 0 0 : 1 1 NW1 0 0 1 1 : 1 1 NW0 0 1 0 1 : 0 1 DESCRIPTION 0-Line Inversion (Frame Inversion) 2-Line Inversion 3-Line Inversion 4-Line Inversion : 15-Line Inversion 16-Line Inversion 0000 RESET STATE 44/66 STE2004 Figure 55. I2C Interface Interconnection in Master/ Slave Mode STE2004 RES SCL SDAOUT SDAIN RES STE2004 SCL SDAOUT SDAIN LR0214 NOTE: MASTER and SLAVE I2C AADDRESS MUST BE DIFFERENT RES SCL SDA Figure 56. I3-lines SPI & 3-lines Serial Interfaces Interconnection in Master Slave Mode STE2004 RES CS SCLK SDIN SDOUT RES CS STE2004 SCLK SDIN SDOUT LR0215 RES MASTER SCLK CS SD SLAVE CS Figure 57. 4-lines SPI Interface Interconnection in Master Slave Mode STE2004 RES CS D/C SCLK SDIN SDOUT RES D/C STE2004 CS SCLK SDIN SDOUT LR0216 RES MASTER D/C CS SCLK SD SLAVE CS 45/66 STE2004 Figure 58. 8080-series & 68000-series Interface Interconnection in Master Slave Mode STE2004 RES CS D/C RW-RD E-WR D7-D0 RES D/C 8 LINES STE2004 CS RW-RD E-WR D7-D0 LR0217 8 LINES RES MASTER D/C CS RW-RD E-WR D7-D0 SLAVE CS Figure 59. Host Processor Interconnection with I2C Interface VSS TEST_MODE STE2004 P VSSAUX D0 D1 D2 D3 D4 D5 D6 D7 SCLK -SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VSSAUX VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX LR0110 46/66 STE2004 Figure 60. Host Processor Interconnection with 4-line SPI Interface VSS TEST_MODE STE2004 P VSSAUX D0 D1 D2 D3 D4 D5 D6 D7 SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VDD1 VSSAUX VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX LR0111 Figure 61. Host Processor Interconnection with 3-line SPI Interface VSS TEST_MODE STE2004 P VSSAUX D0 D1 D2 D3 D4 D5 D6 D7 SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VSSAUX VDD1 VSSAUX VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX LR0112 47/66 STE2004 Figure 62. Host Processor Interconnection with 3-line Serial Interface VSS TEST_MODE STE2004 P VSSAUX D0 D1 D2 D3 D4 D5 D6 D7 SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VDD1 VDD1 VSSAUX VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX LR0113 Figure 63. Host Processor Interconnection with 8080-series Parallel Interface VSS TEST_MODE STE2004 P VSSAUX D0 D1 D2 D3 D4 D5 D6 D7 SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VSSAUX VSSAUX VDD1 VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX LR0114 48/66 STE2004 Figure 64. Host Processor Interconnection with 6800 VSS TEST_MODE STE2004 P VSSAUX D0 D1 D2 D3 D4 D5 D6 D7 SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX E - WR R/W - RD D/C CS RES VDD2 VDD1 ICON SEL1 SEL2 SEL3 EXT_SET M/S SA0 SA1 VSSAUX TEST VREF ANALOG VDD DIGITAL VDD VDD1 / VSSAUX VDD1 VSSAUX VDD1 VDD1 / VSSAUX VDD1 VDD1 / VSSAUX VDD1 / VSSAUX VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX LR0115 49/66 STE2004 Figure 65. Application Schematic using the Internal LCD Voltage Generator and two separate supplies I/O VDD2 VDD1 1F VSS VDD2 VDD1 1F VSS 102 65 x 102 DISPLAY 32 1F VLCDSENSE 33 VLCD Figure 66. Application Schematic using the Internal LCD Voltage Generator and a single supply I/O VDD VDD2 VDD1 32 1F VSS VSS 102 65 x 102 DISPLAY 1F VLCDSENSE 33 VLCD 50/66 STE2004 Figure 67. Power-ON timing diagram Tvdd Tw(res) Tlogic(res) VDD2 VDD1 RES CS SCLK SDIN D/C E R/W D0 - D7 HOST D0 - D7 DRIVER Hi-Z SCL- SDAIN SDOUT SDA OUT Hi-Z OSCIN, FR_IN (HOST) OSC OUT, FR_OUT (DRIVER) RESET POWER ON BOOSTER Acceptance INTERNAL OFF RESET Time LR0208 51/66 STE2004 Figure 68. Power-OFF timing diagram TVDD VDD2 VDD1 RES CLK-SCL SDIN-SDAIN D/C E CS R/W D0 - D7 HOST D0 - D7 DRIVER Hi-Z SDOUT SDA-OUT Hi-Z OSCIN (HOST) OSC OUT FR_OUT (DRIVER) FR_IN RESET TABLE LOADED LR0207 52/66 STE2004 Figure 69. Initialization with built-in Booster SETUP NORMAL DISPLAY MODE CONFIGURATION SET Driver in Power Down(PD=1) SET Driver in Normal Display Mode (PE=0) SET Operative Voltage for Normal Display Operation ( Vop[6:0] - PRS[1;0]) SET Bias Raio for Normal Display Operation (BS[2:0]) SET Temperature Compensation for Normal Display Operation (T[2:0] or TC[1:0]) SET Multiplexing Rate M[1:0) SET Charge Pump for Normal Display Operation (CP[1:0]) Switch "ON" Booster and Display Control Logic (PD=0) END OF NORMAL DISPLAY MODE CONFIG. LR0218 53/66 STE2004 Figure 70. DATA RAM to display Mapping DISPLAY DATA RAM bank 0 GLASS TOP VIEW bank 1 DISPLAY DATA RAM = "1" DISPLAY DATA RAM = "0" bank 2 LCD bank 3 bank 7 bank 8 ICOR ROW D00IN1155 Table 25. Test Pin Configuration Test Pin TEST_VREF TEST_MODE Pin Configuration OPEN GND 54/66 STE2004 Table 26. Absolute Maximum Ratings Symbol VDD1 VDD2 VLCD ISS Vi Iin Iout Ptot Po Tj Tstg Supply Voltage Range Supply Voltage Range LCD Supply Voltage Range Supply Current Input Voltage (all input pads) DC Input Current DC Output Current Total Power Dissipation (Tj = 85C) Power Dissipation per Output Operating Junction Temperature Storage Temperature Parameter Value - 0.5 to + 5 - 0.5 to + 7 - 0.5 to + 15 - 50 to +50 -0.5 to VDD1 + 0.5 - 10 to + 10 - 10 to + 10 300 30 -40 to + 85 - 65 to 150 Unit V V V mA V mA mA mW mW C C Table 27. Electrical Characteristics DC OPERATION (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85C; unless otherwise specified) Symbol Supply Voltages VDD1 VDD2 VLCD I(VDD1) Supply Voltage Supply Voltage LCD Supply Voltage LCD Supply Voltage Supply Current Note 9 LCD Voltage Internally generated LCD Voltage Supplied externally Internally generated; note 1 VDD1 = 2.8V; VLCD = 10V; fsclk = 0;Tamb = 25C; Parallel Port; note 3,8. VDD2 = 2.8V; VLCD = 10V; fsclk = 1Mhz;Tamb = 25C; OSC_IN=GND; Note8. with VOP = 0 and PRS = [0:0] with external VLCD VDD2 = 2.8V; VLCD = 10V; fsclk=0; Tamb = 25C; no display load; 5x charge pump; note 2,3,6, I(VDD1,2) Total Supply Current VDD2 = 2.8V; VLCD = 10V; 5x charge pump; fsclk = 0; Tamb = 25C; no display load; note 2, 3, 6 Power down Mode with internal or External VLCD. Note 4 I(VLDCIN) External LCD Supply Voltage Current VDD =2.8V; VLCD =10V;no display load; fsclk = 0; Tamb = 25C; note 3. IOH=-500A IOL=+500A 0.8VDD1 VSS 60 1.7 1.75 4.5 4.5 15 20 3.6 VDD2 4.5 14.5 14.5 30 V V V V V A Parameter Test Condition Min. Typ. Max. Unit Supply Current Write Mode 100 120 A I(VDD2) Voltage Generator Supply Current 1 100 A A 80 130 A 3 10 23 A A Logic Outputs V0H VOL High logic Level Output Voltage Low logic Level Output Voltage VDD1 0.2VDD1 V V 55/66 STE2004 Table 23 Electrical Characteristics (continued) DC OPERATION (continued) (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85C; unless otherwise specified) Symbol Logic Inputs VIL VIH Iin VIL VIH Logic LOW voltage level Logic HIGH Voltage Level Input Current Logic LOW voltage level Logic HIGH Voltage Level Vin = VSS1 or VDD1 VSS 0.7 VDD1 -1 VSS 0.7 VDD1 3K 5K No load -50 -50 VDD = 2.8V; VLCD = 10V; fsclk=0; Tamb=25 C; no display load;note 2, 3, 6 & 7, VOP=69h, PRS=2Hex -1.8 0.3 VDD1 VDD2 1 0.3 VDD1 VDD1 + 0.5 5K 10K +50 +50 +1.8 V V A V V Parameter Test Condition Min. Typ. Max. Unit Logic Inputs/Outputs Column and Row Driver Rrow Rcol Vcol Vrow VLCD ROW Output Resistance Column Output resistance Column Bias voltage accuracy Row Bias voltage accuracy LCD Supply Voltage accuracy; Internally generated kohm kohm mV mV % LCD Supply Voltage TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Notes: 1. 2. 3. 4. 5. 6. Temperature coefficient -0.0* 10-3 -0.35 * 10-3 -0.7 * 10-3 -1.05* 10-3 -1.4 * 10-3 -1.75* 10-3 -2.1 * 10-3 -2.3* 10-3 1/C 1/C 1/C 1/C 1/C 1/C 1/C 1/C The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load. Internal clock When fsclk = 0 there is no interface clock. Power-down mode. During power-down all static currents are switched-off. If external VLCD, the display load current is not transmitted to IDD Tolerance depends on the temperature; (typically zero at Tamb = 27C), maximum tolerance values are measured at the temperature range limit. 7. For TC0 to TC7 8. Data Byte Writing Mode 9. VDD1<=VDD2 56/66 STE2004 Table 23 Electrical Characteristics (continued) AC OPERATION (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85C; unless otherwise specified) Symbol FOSC FEXT FFRAME Tw(RES) TLOGIC (RES) Parameter Internal Oscillator frequency External Oscillator frequency Frame frequency RES LOW pulse width Reset Pulse Rejection Internal Logic Reset Time VDD1 vs. VDD2 Delay Test Condition VDD = 2.8V; Tamb = -20 to +70 C Min. 63 20 Typ. 72 Max. 81 100 Unit kHz kHz Hz s s s s INTERNAL OSCILLATOR fosc or fext = 72 kHz; note 1 5 75 1 5 0 TVDD Figure 71. RESET timing diagram Tw(res) Tlogic(res) VDD2 VDD1 RES INPUTS I/O (HOST) I/O (DRIVER) INTERFACE OUTPUT OSCIN FR_IN (HOST) OSC OUT FR_OUT (DRIVER) Hi-Z Hi-Z RESET TABLE LOADED LR0209 57/66 STE2004 Table 23 Electrical Characteristics (continued) AC OPERATION (continued) (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85C; unless otherwise specified) Symbol 2 Parameter SCL Clock Frequency Test Condition Fast Mode High Speed Mode; Cb=100pF (max);note 6;VDD1=2 High Speed Mode; Cb=400pF (max);note 6; VDD1=2 Fast Mode; note 6; VDD1=1.7V Min. DC DC DC Typ. Max. 400 3.4 1.7 400 Unit kHz MHz MHz KHz ns ns ns ns ns ns ns ns I C BUS INTERFACE (See note 4, 7) FSCL TSU;STA THD;STA TLOW THIGH TSU;DAT THD;DAT Tr;CL Tr;CL1 Set-up time (repeated) START Condition Hold Time (repeated) START Condition Low Period of SCLH Clock HIGH Period of SCLH Clock Data set-up Time Data Hold Time Rise Time of SCLH Signal Rise Time of SCLH Signal after a repeated START condition and aftyer an Acknowledge bit Fall time of SCLH signal Rise time of SCLH signal Fall time of SDAH signal Rise Time of SDAH signal Fall Time of SDAH signal Setup Time for STOP condition Capacitive Load for SDAH and SCLH Capacitive Load for SDAH +SDA line and SCLH +SCL Line Note 2,3, Cb = 100pF Note 2,3, Cb = 100pF Note 2,3, Cb = 100pF Note 2,3, Cb = 100pF Note 2,3, Cb = 100pF Note 2,3, Cb = 100pF Note 2,3, Cb = 100pF Note 2,3, Cb = 100pF 160 160 160 160 60 10 10 10 Tf;CL Tr;DA Tf;DA Tr;DA Tf;DA TSU;STO Cb Cb Note 2,3, Cb = 100pF Note 2,3, Cb = 100pF Note 2,3, Cb = 100pF Note 2,3, Cb = 400pF Note 2,3, Cb = 400pF Note 2,3, Cb = 100pF 10 10 10 20 20 160 100 400 400 160 80 ns ns ns ns ns ns pF pF Figure 72. I2C-bus timings Sr tfDA trDA Sr P SDAH tHD;DAT tSU;STA SCLH tfCL trCL tHIGH tLOW = MCS current source pull-up tSU;DAT tHD;STA trCL1 (1) trCL1 (1) tLOW tHIGH LR0093 = Rp resistor pull-up 58/66 STE2004 Table 23 Electrical Characteristics (continued) AC OPERATION (continued) (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85C; unless otherwise specified) Symbol TCYC TCLW TCHW TCLR TCHR TEWHW TEWLW TEWHR TEWLR TSU(A) TH(A) TSU1 TH1 TSU2 TH2 Parameter System Cycle Time Control Low Pulse Width (WR) Control High Pulse Width (WR) Control Low Pulse Width (RD) Control High Pulse Width (RD) Enable High Pulse Width (Write) Enable Low Pulse Width (Write) Enable High Pulse Width (Read) Enable Low Pulse Width (Read) Address Set-up Time Address Hold Time Data Set-Up Time Data Hold Time Read Access Time Output Disable Time 0 Test Condition VDD1 = 1.7V; Read & Write Min. 125 20 75 40 55 60 60 60 60 10 10 30 30 40 30 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PARALLEL INTERFACE Figure 73. 68000-series Parallel interface timing D/C R/W tSU(A) CS tH(A) tCYC tEWHR, tEWHW E tEWLR, tEWLW tSU1 D0 to D7 (Write) tH1 tSU2 D0 to D7 (Read) tH2 Figure 74. 8080-series parallel Interface timing D/C tSU(A) CS tH (A) tCYC tCLR , tCLW WR, RD tCHR , tCHW tSU1 D0 to D7 (Write) tH1 tSU2 D0 to D7 (Read) tH2 59/66 STE2004 Table 23 Electrical Characteristics (continued) AC OPERATION (continued) (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85C; unless otherwise specified) Symbol SERIAL INTERFACE FSCLK TCYC TPWH1 TPWL1 TS2 TH2 TPWH2 TS3 TH3 TS4 TH4 TS5 TH5 TH6 Clock Frequency Clock Cycle SCLK SCLK pulse width HIGH SCLK Pulse width LOW CS setup time CS hold time CS minimum high time SD/C setup time SD/C hold time SDIN setup time SDIN hold time SDOUT Access Time SDOUT Disable Time vs. SCLK SDOUT Disable Time vs. CS 0 0 VDD1 = 1.7V VDD1 = 1.7V; 8 125 60 60 40 50 50 30 30 30 40 30 20 20 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Test Condition Min. Typ. Max. Unit Figure 75. Serial interface Timing tS2 CS tS3 D/C tCYC tPWL1 SCLK tS4 SDIN tS5 SOUT LR0096 tH2 tPWH2 tH3 tWH1 tS2 tH4 tH5 tH6 Notes: 1. F frame = --------960 2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with an input voltage swing of VSS to VDD 3. Cb is the capacitive load for each bus line. 4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated 5. CVLCD is the filtering CApacitor on VLCD 6. Trise and Tfall (30%-70%) -10ns 7. I2C bus AC Characteristics are tested by correlation f osc 60/66 STE2004 Table 28. Pad Coordinates NAME R5 R4 R3 R2 R1 R0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 X (m) -2925.0 -2875.0 -2825.0 -2775.0 -2725.0 -2675.0 -2625.0 -2575.0 -2525.0 -2475.0 -2425.0 -2375.0 -2325.0 -2275.0 -2225.0 -2175.0 -2125.0 -2075.0 -2025.0 -1975.0 -1925.0 -1875.0 -1825.0 -1775.0 -1725.0 -1675.0 -1625.0 -1575.0 -1525.0 -1475.0 -1425.0 Y(m) -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 Table 28. Pad Coordinates (continued) NAME C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 PAD 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 X (m) -1375.0 -1325.0 -1275.0 -1225.0 -1175.0 -1125.0 -1075.0 -1025.0 -975.0 -925.0 -875.0 -825.0 -775.0 -725.0 -675.0 -625.0 -575.0 -525.0 -475.0 -425.0 -375.0 -325.0 -275.0 -225.0 -175.0 -125.0 125.0 175.0 225.0 275.0 325.0 Y(m) -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 61/66 STE2004 Table 28. Pad Coordinates (continued) NAME C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 PAD 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 X (m) 375.0 425.0 475.0 525.0 575.0 625.0 675.0 725.0 775.0 825.0 875.0 925.0 975.0 1025.0 1075.0 1125.0 1175.0 1225.0 1275.0 1325.0 1375.0 1425.0 1475.0 1525.0 1575.0 1625.0 1675.0 1725.0 1775.0 1825.0 1875.0 Y(m) -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 Table 28. Pad Coordinates (continued) NAME C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 PAD 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 X (m) 1925.0 1975.0 2025.0 2075.0 2125.0 2175.0 2225.0 2275.0 2325.0 2375.0 2425.0 2475.0 2525.0 2575.0 2625.0 2675.0 2725.0 2775.0 2825.0 2875.0 2925.0 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 Y(m) -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -596.5 -525.0 -475.0 -425.0 -375.0 -325.0 -275.0 -225.0 -175.0 -125.0 -75.0 62/66 STE2004 Table 28. Pad Coordinates (continued) NAME R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64-ICON VDD1_AUX FR_IN OSC_IN VSENSE_SLAVE TEST_VREF VSSAUX SA1 SA0 M/S EXT_SET SEL3 SEL2 SEL1 ICON PAD 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 X (m) 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 3086.5 2925.0 2875.0 2825.0 2775.0 2725.0 2475.0 2425.0 2375.0 2325.0 1975.0 1925.0 1875.0 1825.0 1775.0 1725.0 1675.0 1625.0 1575.0 1525.0 Y(m) -25.0 25.0 75.0 125.0 175.0 225.0 275.0 325.0 375.0 425.0 475.0 525.0 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 Table 28. Pad Coordinates (continued) NAME VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 RES CS D/C R/W - RD E - WR VSSAUX SDAOUT SDIN-SDAIN SDOUT SCLK-SCL D7 D6 D5 D4 D3 PAD 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 X (m) 1475.0 1425.0 1375.0 1325.0 1275.0 1225.0 1175.0 1125.0 1075.0 1025.0 975.0 925.0 875.0 825.0 775.0 725.0 375.0 275.0 175.0 75.0 -25.0 -75.0 -175.0 -225.0 -275.0 -375.0 -425.0 -475.0 -525.0 -575.0 -625.0 Y(m) 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 63/66 STE2004 Table 28. Pad Coordinates (continued) NAME D2 D1 D0 VSSAUX TEST_MODE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VLCDSENSE VLCD VLCD VLCD VLCD VLCD OSC_OUT FR_OUT R31 R30 R29 R28 R27 PAD 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 X (m) -675.0 -725.0 -775.0 -825.0 -1225.0 -1275.0 -1325.0 -1375.0 -1425.0 -1475.0 -1525.0 -1575.0 -1625.0 -1675.0 -1725.0 -1775.0 -1825.0 -2075.0 -2125.0 -2175.0 -2225.0 -2275.0 -2325.0 -2475.0 -2525.0 -2775.0 -2825.0 -2875.0 -2925.0 -3086.5 Y(m) 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 596.5 525.0 Table 28. Pad Coordinates (continued) R26 NAME R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 217 PAD 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 -3086.5 X (m) -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 -3086.5 475.0 Y(m) 425.0 375.0 325.0 275.0 225.0 175.0 125.0 75.0 25.0 -25.0 -75.0 -125.0 -175.0 -225.0 -275.0 -325.0 -375.0 -425.0 -475.0 -525.0 Table 29. Alignment marks coordinates MARKS mark1 mark2 mark3 mark4 X -3089.5 3089.5 -2400.0 538.1 Y -599.5 -599.5 599.5 599.5 64/66 STE2004 Figure 76. Alignment marks dimensions Table 30. Bumps Bump Number Bumps Size Pad Size Pad Pitch 39 m 94 m Dimensions 30m X 98 m X 17.5 43m X 107m 50m 20m Spacing between Bumps Table 31. Die Mechanical Dimensions Die Size (X x Y) Wafers Thickness 6.42mm x 1.46mm 500m Table 32. Revision History Date May 2004 July 2004 Revision 3 4 Description of Changes Moved the value of FSCLK parameter from Min. to Max. on the page 60/ 66. Inserted Table 24 -N-Line Inversion in the page 44/66 65/66 STE2004 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 66/66 |
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